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nightmodeapiarchive

bad_top.v

nightmodeapiarchive
Jul 18th, 2024 (edited)
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SystemVerilog 0.57 KB | None | 0 0
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  1. module top
  2. (
  3.     input SPIMOSI,
  4.     input SPICLK,
  5.     input SPICS,
  6.     input SYSCLK,
  7.     input btnA,
  8.     output VGA_VSYNC,
  9.     output VGA_HSYNC,
  10.     output VGA_R,
  11.     output VGA_G,
  12.     output VGA_B
  13. );
  14. wire MAIN_CLK;
  15. wire VSYNC;
  16. wire HSYNC;
  17. wire RED;
  18. Gowin_rPLL PLL_INST(
  19.     .clkout(MAIN_CLK),           //output clkout(~200.5mhz)
  20.     .clkin(SYSCLK)               //input clkin(27mhz)
  21. );
  22. vga VGA_INST(
  23.     .CLK(MAIN_CLK),
  24.     .VSYNC(VSYNC),
  25.     .R(RED),
  26.     .HSYNC(HSYNC)
  27. );
  28. assign VGA_HSYNC = HSYNC;
  29. assign VGA_VSYNC = VSYNC;
  30. assign VGA_R = RED;
  31. endmodule
  32.  
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