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- # -------------------------------------------------------------------------- #
- #
- # Copyright (C) 1991-2009 Altera Corporation
- # Your use of Altera Corporation's design tools, logic functions
- # and other software and tools, and its AMPP partner logic
- # functions, and any output files from any of the foregoing
- # (including device programming or simulation files), and any
- # associated documentation or information are expressly subject
- # to the terms and conditions of the Altera Program License
- # Subscription Agreement, Altera MegaCore Function License
- # Agreement, or other applicable license agreement, including,
- # without limitation, that your use is for the sole purpose of
- # programming logic devices manufactured by Altera and sold by
- # Altera or its authorized distributors. Please refer to the
- # applicable agreement for further details.
- #
- # -------------------------------------------------------------------------- #
- #
- # Quartus II
- # Version 9.1 Build 222 10/21/2009 SJ Full Version
- # Date created = 17:27:31 April 30, 2010
- #
- # -------------------------------------------------------------------------- #
- #
- # Notes:
- #
- # 1) The default values for assignments are stored in the file:
- # nisetroi_assignment_defaults.qdf
- # If this file doesn't exist, see file:
- # assignment_defaults.qdf
- #
- # 2) Altera recommends that you do not modify this file. This
- # file is updated automatically by the Quartus II software
- # and any changes you make may be lost or overwritten.
- #
- # -------------------------------------------------------------------------- #
- set_global_assignment -name FAMILY "MAX II"
- set_global_assignment -name DEVICE EPM570T100C3
- set_global_assignment -name TOP_LEVEL_ENTITY nisetroi
- set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.1
- set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:27:31 APRIL 30, 2010"
- set_global_assignment -name LAST_QUARTUS_VERSION 9.1
- set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
- set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
- set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
- set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V
- set_global_assignment -name VERILOG_FILE nisetroi.v
- set_global_assignment -name MISC_FILE "d:/nisetro/nisetroi.dpf"
- set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
- set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
- set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
- set_location_assignment PIN_17 -to ADDR[0]
- set_location_assignment PIN_16 -to ADDR[1]
- set_location_assignment PIN_15 -to ADDR[2]
- set_location_assignment PIN_8 -to DIR
- set_location_assignment PIN_35 -to FX2_FD[0]
- set_location_assignment PIN_36 -to FX2_FD[1]
- set_location_assignment PIN_38 -to FX2_FD[2]
- set_location_assignment PIN_40 -to FX2_FD[3]
- set_location_assignment PIN_34 -to FX2_FD[4]
- set_location_assignment PIN_33 -to FX2_FD[5]
- set_location_assignment PIN_30 -to FX2_FD[6]
- set_location_assignment PIN_29 -to FX2_FD[7]
- set_location_assignment PIN_20 -to FX2_FIFOADR[0]
- set_location_assignment PIN_19 -to FX2_FIFOADR[1]
- set_location_assignment PIN_28 -to FX2_FLAGA
- set_location_assignment PIN_27 -to FX2_FLAGB
- set_location_assignment PIN_26 -to FX2_FLAGC
- set_location_assignment PIN_18 -to FX2_PKTEND
- set_location_assignment PIN_21 -to FX2_SLOE
- set_location_assignment PIN_5 -to FX2_SLRD
- set_location_assignment PIN_6 -to FX2_SLWR
- set_location_assignment PIN_14 -to FX2_IFCLK
- set_location_assignment PIN_3 -to MODE[0]
- set_location_assignment PIN_4 -to MODE[1]
- set_location_assignment PIN_7 -to RESET
- set_location_assignment PIN_70 -to LCDG1[0]
- set_location_assignment PIN_71 -to LCDG1[1]
- set_location_assignment PIN_75 -to LCDG1[5]
- set_location_assignment PIN_74 -to LCDG1[4]
- set_location_assignment PIN_73 -to LCDG1[3]
- set_location_assignment PIN_72 -to LCDG1[2]
- set_location_assignment PIN_62 -to CLK
- set_location_assignment PIN_67 -to Vsync
- set_location_assignment PIN_66 -to Hsync
- set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to Vsync
- set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to Hsync
- set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to CLK
- set_location_assignment PIN_76 -to LCDG2[5]
- set_location_assignment PIN_77 -to LCDG2[4]
- set_location_assignment PIN_78 -to LCDG2[3]
- set_location_assignment PIN_81 -to LCDG2[2]
- set_location_assignment PIN_82 -to LCDG2[1]
- set_location_assignment PIN_83 -to LCDG2[0]
- set_location_assignment PIN_51 -to LCDB1[5]
- set_location_assignment PIN_84 -to LCDR2[5]
- set_location_assignment PIN_85 -to LCDR2[4]
- set_location_assignment PIN_86 -to LCDR2[3]
- set_location_assignment PIN_87 -to LCDR2[2]
- set_location_assignment PIN_89 -to LCDR2[1]
- set_location_assignment PIN_91 -to LCDR2[0]
- set_location_assignment PIN_99 -to LCDB2[0]
- set_location_assignment PIN_92 -to LCDB2[5]
- set_location_assignment PIN_95 -to LCDB2[4]
- set_location_assignment PIN_96 -to LCDB2[3]
- set_location_assignment PIN_97 -to LCDB2[2]
- set_location_assignment PIN_98 -to LCDB2[1]
- set_location_assignment PIN_50 -to LCDB1[4]
- set_location_assignment PIN_49 -to LCDB1[3]
- set_location_assignment PIN_48 -to LCDB1[2]
- set_location_assignment PIN_47 -to LCDB1[1]
- set_location_assignment PIN_44 -to LCDB1[0]
- set_location_assignment PIN_57 -to LCDR1[5]
- set_location_assignment PIN_56 -to LCDR1[4]
- set_location_assignment PIN_55 -to LCDR1[3]
- set_location_assignment PIN_54 -to LCDR1[2]
- set_location_assignment PIN_53 -to LCDR1[1]
- set_location_assignment PIN_52 -to LCDR1[0]
- set_location_assignment PIN_64 -to SND_MCLK
- set_location_assignment PIN_58 -to SND_WS
- set_location_assignment PIN_61 -to SND_SDO
- set_location_assignment PIN_41 -to SOUT
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