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flip_floopOG

Apr 25th, 2024 (edited)

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output1 = [0] * 32768
output2 = [0] * 32768
output3 = [0] * 32768
# define opcodes
NOP = 0b00000000
LDA = 0b00000001
ADD = 0b00000010
SUB = 0b00000011
STA = 0b00000100
LDI = 0b00000101
JMP = 0b00000110
JZ = 0b00000111
JC = 0b00001000
ADI = 0b00001001
INC = 0b00001010
DEC = 0b00001011
OUT = 0b00001110
MEO = 0b00001100
HALT = 0b00001111
# define control signals
HLT = 0b000000010000000000000000
MI = 0b000000100000000000000000
RI = 0b000001000000000000000000
RO = 0b000010000000000000000000
IO = 0b000100000000000000000000
II = 0b001000000000000000000000
AI = 0b010000000000000000000000
AO = 0b100000000000000000000000
EO = 0b000000000000000100000000
SU = 0b000000000000001000000000
BI = 0b000000000000010000000000
OI = 0b000000000000100000000000
CE = 0b000000000001000000000000
CO = 0b000000000010000000000000
J = 0b000000000100000000000000
FI = 0b000000001000000000000000
MR = 0b000000000000000010000000 # Microcode reset
STO = 0b000000000000000001000000 # Stack Out
STI = 0b000000000000000000100000 # Stack In
STIN = 0b000000000000000000010000 # Stack Increase
STDC = 0b000000000000000000001000 # Stack Decrease
# define CPU flags EEPROM address bits
CF_ADDR_BIT = 13
ZF_ADDR_BIT = 12
# define microcode array
microcode = [
[NOP, MI|CO, RO|II|CE|MR], # 00000000 NOP
[LDA, MI|CO, RO|II|CE, IO|MI, RO|AI|MR], # 00000001 LDA
[ADD, MI|CO, RO|II|CE, IO|MI, RO|BI, EO|AI|FI|MR], # 00000010 ADD
[SUB, MI|CO, RO|II|CE, IO|MI, RO|BI, EO|AI|SU|FI|MR], # 00000011 SUB
[STA, MI|CO, RO|II|CE, IO|MI, AO|RI|MR], # 00000100 STA
[LDI, MI|CO, RO|II|CE, IO|AI|MR], # 00000101 LDI
[JMP, MI|CO, RO|II|CE, IO|J|MR], # 00000110 JMP
[JZ, MI|CO, RO|II|CE|MR], # 00000111 JZ
[JC, MI|CO, RO|II|CE|MR], # 00001000 JC
[ADI, MI|CO, RO|II|CE, IO|BI, EO|AI|FI|MR], # 00001001 ADI
[MEO, MI|CO, RO|II|CE, IO|MI, RO|OI|MR], # 00001100 OUT
[OUT, MI|CO, RO|II|CE, AO|OI|MR], # 00001110 OUT
[HALT, MI|CO, RO|II|CE, HLT] # 00001111 HLT
]
# populate ROM with the first two micro-instruction stages for all possible opcodes
for i in range(4096):
address = i << 3
output1[address] = ((MI|CO) & 0xFF0000) >> 16
output1[address+1] = ((RO|II|CE) & 0xFF0000) >> 16
output2[address] = ((MI|CO) & 0x00FF00) >> 8
output2[address+1] = ((RO|II|CE) & 0x00FF00) >> 8
output3[address] = ((MI|CO) & 0x0000FF)
output3[address+1] = ((RO|II|CE) & 0x0000FF)
# load ROM with micro-instructions
for cf in [0,1]:
for zf in [0,1]:
# calculate base address as a function of CF and ZF
base_addr = (cf * 2 ** CF_ADDR_BIT) | (zf * 2 ** ZF_ADDR_BIT)
# set up JC microcode according to CF flag value
if cf == 1:
# override default JC micro-code for CF = 1
microcode[8] = [JC, MI|CO, RO|II|CE, IO|J]
else:
microcode[8] = [JC, MI|CO, RO|II|CE]
# set up JZ microcode according to ZF flag value
if zf == 1:
# override default JZ micro-code for ZF = 1
microcode[7] = [JZ, MI|CO, RO|II|CE, IO|J]
else:
microcode[7] = [JZ, MI|CO, RO|II|CE]
# populate micro-code
for inst in microcode:
opCode = inst[0]
signals = inst[1:]
for stage, signal in enumerate(signals):
address = base_addr | (opCode << 3) | stage
output1[address] = (signal & 0xFF0000) >> 16
output2[address] = (signal & 0x00FF00) >> 8
output3[address] = (signal & 0x0000FF)
with open('eeprom1.bin', 'wb') as file1:
for x in output1:
file1.write(x.to_bytes(1, byteorder='big', signed=False))
with open('eeprom2.bin', 'wb') as file2:
for x in output2:
file2.write(x.to_bytes(1, byteorder='big', signed=False))
with open('eeprom3.bin', 'wb') as file3:
for x in output3:
file3.write(x.to_bytes(1, byteorder='big', signed=False))

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