API tools faq
paste
Advertisement
gur111

mux4_test.sv

gur111
May 27th, 2020
1,649
0
Never
Add comment
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
SystemVerilog 0.64 KB | None | 0 0
raw download clone embed print report
  1. // 4->1 multiplexer test bench template
  2. module mux4_test;
  3.     logic d0;
  4.     logic d1;
  5.     logic d2;
  6.     logic d3;
  7.     logic [1:0] sel;
  8.     logic z;
  9.    
  10.     localparam B=10,C=6,D=6,E=3,F=1,G=8;
  11.  
  12.     initial begin
  13.         d0 = 1'b0;
  14.         d1 = 1'b0;
  15.         d2 = 1'b0;
  16.         d3 = 1'b0;
  17.         sel[0] = 1'b0;
  18.         sel[1] = 1'b0;
  19.        
  20.         #100;
  21.         d0 = 1'b1;
  22.         #100;
  23.         d0 = 1'b0;
  24.         #100;
  25.  
  26.     end
  27.  
  28.     mux4 #(.B(B), .C(C), .D(D), .E(E), .F(F), .G(G)) mux (
  29.         .z(z),
  30.         .sel(sel),
  31.         .d0(d0),  
  32.         .d1(d1),
  33.         .d2(d2),
  34.         .d3(d3)
  35.     );
  36.  
  37.  
  38.  
  39. endmodule
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement
Public Pastes
Advertisement
We use cookies for various purposes including analytics. By continuing to use Pastebin, you agree to our use of cookies as described in the Cookies Policy.  OK, I Understand
Not a member of Pastebin yet?
Sign Up, it unlocks many cool features!