2. domaci

K1SR

Nov 18th, 2022

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library ieee;
use ieee.std_logic_1164.all;
library work;
entity lprs1_homework2_tb is
end entity;
architecture arch of lprs1_homework2_tb is
constant i_clk_period : time := 25 ns; -- 40 MHz
signal i_clk : std_logic;
signal i_rst : std_logic;
signal i_run : std_logic;
signal i_pause : std_logic;
signal o_digit0 : std_logic_vector(3 downto 0);
signal o_digit1 : std_logic_vector(3 downto 0);
signal o_digit2 : std_logic_vector(3 downto 0);
signal o_digit3 : std_logic_vector(3 downto 0);
begin
uut: entity work.lprs1_homework2
port map(
i_clk => i_clk,
i_rst => i_rst,
i_run => i_run,
i_pause => i_pause,
o_digit0 => o_digit0,
o_digit1 => o_digit1,
o_digit2 => o_digit2,
o_digit3 => o_digit3
);
clk_p: process
begin
i_clk <= '1';
wait for i_clk_period/2;
i_clk <= '0';
wait for i_clk_period/2;
end process;
stim_p: process
begin
-- Test cases:
i_run <= '0';
i_pause <= '0';
i_rst <= '1';
wait for 1000ns-i_clk_period;
i_rst <= '0';
wait for i_clk_period;
i_run <= '1';
wait for i_clk_period;
i_run <= '0';
--1025ns
-------------------------------------
wait for 3000ns-i_clk_period-i_clk_period-i_clk_period;
i_pause <= '1';
--3950ns
wait for i_clk_period;
i_pause <= '0';
i_run <= '1';
wait for i_clk_period;
i_run <= '0';
wait for i_clk_period;
i_run <= '1';
--4025ns
wait for 1000ns;
i_rst <= '1';
wait for 1000ns-i_clk_period;
--6000ns s_en_1us=1
i_rst <= '0';
wait for 33000ns+i_clk_period;
i_rst <= '1';
--39025ns
wait for i_clk_period;
i_rst <= '0';
--39050ns
wait for 24000ns+i_clk_period;
i_rst <= '1';
wait for i_clk_period;
i_rst <= '0';
wait for i_clk_period;
i_rst<='1';
wait for i_clk_period;
i_rst <= '0';
wait;
end process;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- Libraries.
entity lprs1_homework2 is
port(
i_clk : in std_logic;
i_rst : in std_logic;
i_run : in std_logic;
i_pause : in std_logic;
o_digit0 : out std_logic_vector(3 downto 0);
o_digit1 : out std_logic_vector(3 downto 0);
o_digit2 : out std_logic_vector(3 downto 0);
o_digit3 : out std_logic_vector(3 downto 0)
);
end entity;
architecture arch of lprs1_homework2 is
-- Signals.
signal s_en_1us: std_logic;
signal s_tc_1us : std_logic;
signal s_cnt_1us: std_logic_vector (7 downto 0);
signal s_en0 : std_logic;
signal s_tc0 : std_logic;
signal s_cnt0 : std_logic_vector (3 downto 0);
signal s_en1 : std_logic;
signal s_cnt1 : std_logic_vector (3 downto 0);
signal s_tc1 : std_logic;
begin
-- Body.
--Stoperica
process (i_clk, i_rst) begin
if(i_rst = '1') then
s_en_1us <='0';
elsif(rising_edge(i_clk)) then
if(i_run = '1') then
s_en_1us <= '1';
elsif(i_pause = '1') then
s_en_1us <= '0';
end if;
end if;
end process;
--Brojac mikrosekunde-moduo 40
process (i_clk, i_rst) begin
if(i_rst = '1') then
s_cnt_1us <= "00000000";
elsif(rising_edge(i_clk)) then
if(s_en_1us = '1') then
if(s_cnt_1us = 39) then
s_cnt_1us <="00000000";
else
s_cnt_1us <= s_cnt_1us + 1;
end if;
end if;
end if;
end process;
s_tc_1us <= '1' when s_cnt_1us = 39 else
'0';
s_en0 <= '1' when s_en_1us = '1' and s_tc_1us = '1' else
'0';
--Brojac jedne nulte cifre
process (i_clk, i_rst) begin
if(i_rst = '1') then
s_cnt0 <= "0000";
elsif(rising_edge(i_clk)) then
if(s_en0 = '1') then
if(s_cnt0 = "1001") then
s_cnt0 <= "0000";
else
s_cnt0 <= s_cnt0 + 1;
end if;
end if;
end if;
end process;
s_tc0 <= '1' when s_cnt0 ="1001" else
'0';
s_en1 <= '1' when s_tc0 = '1' and s_en0 = '1' else
'0';
o_digit0 <= s_cnt0;
--Brojac jedne prve cifre
process (i_clk, i_rst) begin
if(i_rst = '1') then
s_cnt1 <= "0000";
elsif(rising_edge(i_clk)) then
if(s_en1 = '1') then
if(s_cnt1 = "0110") then
s_cnt1 <= "0000";
else
s_cnt1 <= s_cnt1 + 1;
end if;
end if;
end if;
end process;
s_tc1 <= '1' when s_cnt1 = "0110" else
'0';
o_digit1 <= s_cnt1;
o_digit2 <= "0001";
o_digit3 <= "1100";
end architecture;

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