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- module vga
- (
- input [2:0]D,
- input CLK,
- output [14:0]mem_addr,
- output mem_clk,
- output mem_CE,
- output VSYNC,
- output HSYNC,
- output R,
- output G,
- output B
- );
- reg [2:0]freq_div_counter;
- reg [9:0] vcounter;
- reg [9:0] hcounter;
- wire RED;
- wire GREEN;
- wire BLUE;
- wire DISPLAY;
- assign R = RED & DISPLAY;
- assign G = GREEN & DISPLAY;
- assign B = BLUE & DISPLAY;
- assign RED = 1;
- assign DISPLAY = (hcounter <= 639 && vcounter <= 479) ? 1'b1 : 1'b0;
- assign HSYNC = (hcounter >= 656 && hcounter <= 752) ? 1'b0 : 1'b1;
- assign VSYNC = (vcounter >= 490 && vcounter <= 492) ? 1'b0 : 1'b1;
- always @(posedge CLK) begin
- if(freq_div_counter == 7) begin
- if(hcounter == 800) begin
- hcounter <= 0;
- if(vcounter == 525) begin
- vcounter <= 0;
- end else begin
- vcounter <= vcounter + 1;
- end;
- end else begin
- hcounter <= hcounter + 1;
- end;
- end;
- freq_div_counter <= freq_div_counter + 1;
- end
- endmodule
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