Sidsh's Pastebin

1,063 37,143 0 3 years ago

Name / Title	Added	Expires	Hits	Syntax
Untitled	Dec 4th, 2024	Never	6,308	SystemVerilog	-
Untitled	Dec 1st, 2024	Never	76	None	-
function cache rajni	Dec 1st, 2024	Never	534	SystemVerilog	-
Untitled	Nov 8th, 2024	Never	87	None	-
Untitled	Nov 2nd, 2022	Never	435	None	-
Reporting system	Oct 29th, 2022	Never	1,418	SystemVerilog	-
sequencer.sv	Oct 29th, 2022	Never	1,430	SystemVerilog	-
monitor.sv	Oct 29th, 2022	Never	1,514	SystemVerilog	-
driver.sv	Oct 29th, 2022	Never	1,499	SystemVerilog	-
interface.sv	Oct 29th, 2022	Never	1,368	SystemVerilog	-
sequence.sv	Oct 29th, 2022	Never	1,603	SystemVerilog	-
sequence_item.sv	Oct 29th, 2022	Never	1,545	SystemVerilog	-
agent.sv	Oct 29th, 2022	Never	1,405	SystemVerilog	-
env.sv	Oct 29th, 2022	Never	1,438	SystemVerilog	-
test.sv	Oct 29th, 2022	Never	1,366	SystemVerilog	-
top.sv	Oct 29th, 2022	Never	1,316	SystemVerilog	-
Haskell blinker.	Jun 26th, 2022	Never	499	Haskell	-
Haskell Blinker	Jun 26th, 2022	Never	234	None	-
Haskell Blinker	Jun 26th, 2022	Never	453	Haskell	-
Blinker Haskell;	Jun 26th, 2022	Never	373	Haskell	-
WB_pwmaudiocontroller	Apr 10th, 2022	Never	916	SystemVerilog	-
Counter	Mar 25th, 2022	Never	228	None	-
LSA Documented 2.0	Mar 3rd, 2022	Never	393	VeriLog	-
LED Documented (sec*) 2.0	Mar 3rd, 2022	Never	227	None	-
ADC Documented 2.0	Mar 3rd, 2022	Never	399	VeriLog	-
LSA Documented 1.1	Mar 3rd, 2022	Never	412	VeriLog	-
LED Documented (sec*)	Mar 3rd, 2022	Never	393	VeriLog	-
ADC Documented	Mar 3rd, 2022	Never	269	VeriLog	-
UART messages added to Pick and Place+e	Mar 3rd, 2022	Never	250	VeriLog	-
Untitled	Mar 3rd, 2022	Never	251	VeriLog	-
Electromagnet enabled LSA	Mar 1st, 2022	Never	294	VeriLog	-
SM Path+Dep 1.2	Mar 1st, 2022	Never	243	VeriLog	-
Path Traversal+Deposition SM	Feb 28th, 2022	Never	259	VeriLog	-
SM Path Traversal 1.1	Feb 28th, 2022	Never	261	VeriLog	-
Path Traversal SM	Feb 27th, 2022	Never	269	VeriLog	-
Dijkstra Sep	Feb 11th, 2022	Never	318	VeriLog	-
Dijkstra_only	Feb 11th, 2022	Never	225	VeriLog	-
LSA Backup	Feb 10th, 2022	Never	247	None	-
LSA Hardcoded	Feb 10th, 2022	Never	255	VeriLog	-
LSA Hardcoded TB	Feb 10th, 2022	Never	250	VeriLog	-
Hardcoded LSA	Feb 10th, 2022	Never	269	VeriLog	-
Untitled	Feb 9th, 2022	Never	252	VeriLog	-
Untitled	Feb 9th, 2022	Never	251	VeriLog	-
LSA+Dijkstra 2.0	Feb 9th, 2022	Never	254	VeriLog	-
Dijkstra+LSA	Feb 8th, 2022	Never	243	VeriLog	-
Dijkstra Reference	Feb 7th, 2022	Never	253	VeriLog	-
Dijkstra tb	Feb 6th, 2022	Never	251	VeriLog	-
Dijkstra	Feb 6th, 2022	Never	247	VeriLog	-
Dijkstra without input data	Feb 5th, 2022	Never	228	VeriLog	-
Dijkstra without input data	Feb 5th, 2022	Never	226	VeriLog	-
Untitled	Feb 5th, 2022	Never	247	VeriLog	-
Dijkstra rough	Feb 4th, 2022	Never	239	VeriLog	-
Untitled	Feb 4th, 2022	Never	222	VeriLog	-
Untitled	Feb 4th, 2022	Never	235	C++	-
Untitled	Feb 4th, 2022	Never	222	VeriLog	-
LED	Feb 1st, 2022	Never	231	VeriLog	-
LED	Feb 1st, 2022	Never	229	VeriLog	-
LED	Feb 1st, 2022	Never	208	None	-
LED_tb	Feb 1st, 2022	Never	223	VeriLog	-
Untitled	Jan 31st, 2022	Never	224	VeriLog	-
Stop logic LSA	Jan 31st, 2022	Never	246	VeriLog	-
Stop logic LSA	Jan 31st, 2022	Never	209	VeriLog	-
Stop logic LSA	Jan 31st, 2022	Never	246	VeriLog	-
Untitled	Jan 31st, 2022	Never	203	None	-
Documented LSA	Jan 31st, 2022	Never	241	VeriLog	-